SOFTWARE

Martin O'Hara , in EMC at Component and PCB Level, 1998

8.1.two Refresh Port Connections

The data direction registers and the input/output port data registers are ordinarily located nearly the edge of the processor'due south package if included in the microprocessor and may be connected straight to the external circuits. Consequently, these are highly probable to take dissonance on their lines. A simple way of minimising this noise disturbing the data settings and propagating into the microprocessor integrated circuit (IС) or system is to refresh these registers regularly.

The action of the microprocessor rewriting these data registers stabilises the interfaced circuits and minimises the risk that noise on these ports is corrupting other internal registers. This is a simple task to perform regularly and involves minimal programming overhead, just occasional write commands to the ports and data registers.

Some intendance does need exercising to ensure that writing the port status is appropriate to the program activeness at each re-write command. Information technology tin can not be causeless that the value in the port status is the correct setting then a read and and so re-write could result in enforcing an erroneous setting.

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PIC Programming

Martin Bates , in Interfacing Flick Microcontrollers (Second Edition), 2014

two.4.ii.i TRIS

This was an pedagogy originally provided to brand port initialisation simpler (encounter program LED1). It selects annals bank 1 so that the TRIS data direction registers (TRISA, TRISB, etc.) can exist loaded with a information direction code (0=output). The manufacturer no longer recommends use of this instruction, although it is even so supported by the current assembler versions and is useful when learning with very uncomplicated programs. The assembler directive BANKSEL should exist used in almost programs, because it gives access to all the registers in banks 1, 2 and 3. The other pick is to modify the bank select bits RP0 and RP1 explicitly in the STATUS register direct, using BSF and BCF.

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Motion picture Programme Development

Martin Bates , in Picture show Microcontrollers (Third Edition), 2011

4.5.two Port Initialization

TRIS   portb

Port B is used every bit the output for the 8-bit binary count. The information direction must be set using the TRIS command, which loads the port data direction annals with the data direction code. In this example, the lawmaking is given in binary, b'00000000'. This is useful, especially if the port bits are to exist set equally a mixture of inputs and outputs; the binary code identifies the data direction for each bit individually. This code is loaded into W using MOVLW, and the TRIS command follows.

The TRIS didactics is however available equally a simple way of initializing the ports, but the manufacturers recommend an alternative method, which involves bank selection, and volition exist covered subsequently. Hopefully, TRIS will proceed to be supported in by the MPASM assembler, equally information technology is easier for beginners.

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PIC18F Microcontroller Series

Dogan Ibrahim , in SD Carte Projects Using the Pic Microcontroller, 2010

PORTC, D, Due east, and Beyond

In addition to PORTA and PORTB, PIC18F452 has 8-bit bidirectional ports PORTC and PORTD, and 3-bit PORTE. Each port has its ain data register (e.m., PORTC), information direction register (e.thousand., TRISC), and data latch annals (e.yard., LATC). The general operation of these ports is similar to PORTA.

In the PIC18F452 microcontroller, PORTC is multiplexed with several peripheral functions, as shown in Table ii.8. On a POR, PORTC pins are configured as digital inputs.

Tabular array 2.viii. PIC18F452 PORTC Pin Functions

Pin Description
RC0/T1OSO/T1CKI
RC0 Digital I/O
T1OSO Timer 1 oscillator output
T1CKI Timer 1/Timer iii external clock input
RC1/T1OSI/CCP2
RC1 Digital I/O
T1OSI Timer 1 oscillator input
CCP2 Capture 2 input, Compare 2 and PWM2 output
RC2/CCP1
RC2 Digital I/O
CCP1 Capture 1 input, Compare 1 and PWM1 output
RC3/SCK/SCL
RC3 Digital I/O
SCK Synchronous serial clock input/output for SPI
SCL Synchronous series clock input/output for I2C
RC4/SDI/SDA
RC4 Digital I/O
SDI SPI data input
SDA I2C data I/O
RC5/SDO
RC5 Digital I/O
SDO SPI data output
RC6/TX/CK
RC6 Digital I/O
TX USART transmit pivot
CK USART synchronous clock pin
RC7/RX/DT
RC7 Digital I/O
RX USART receive pin
DT USART synchronous data pin

In the PIC18F452 microcontroller, PORTD has Schmitt Trigger input buffers. On a POR, PORTD is configured as digital inputs. PORTD can be configured as an 8-flake PSP (i.east., microprocessor port) by setting scrap 4 of the TRISE register. Tabular array 2.9 shows functions of PORTD pins.

Table 2.9. PIC18F452 PORTD Pin Functions

Pin Description
RD0/PSP0
RD0 Digital I/O
PSP0 Parallel Slave Port bit 0
RA0 RD1/PSP1
RD1 Digital I/O
PSP1 Parallel Slave Port bit 1
RD2/PSP2
RD2 Digital I/O
PSP2 Parallel Slave Port fleck ii
RD3/PSP3
RD3 Digital I/O
PSP3 Parallel Slave Port bit 3
RD4/PSP4
RD4 Digital I/O
PSP4 Parallel Slave Port bit 4
RD5/PSP5
RD5 Digital I/O
PSP5 Parallel Slave Port flake 5
RD6/PSP6
RD6 Digital I/O
PSP6 Parallel Slave Port fleck 6
RD7/PSP7
RD7 Digital I/O
PSP7 Parallel Slave Port bit 7

In the PIC18F452 microcontroller, PORTE is only 3 bits broad. As shown in Table ii.10, port pins are shared with analog inputs and parallel slave port read/write control $.25. On a POR, PORTE pins are configured as analog inputs, and register ADCON1 must be programmed to change these pins to digital I/O.

Table 2.10. PIC18F452 PORTE Pin Functions

Pin Clarification
RE0/RD/AN5
RE0 Digital I/O
RD Parallel Slave Port read control pin
AN5 Analog input 5
RE1/WR/AN6
RE1 Digital I/O
WR Parallel Slave Port write control pivot
AN6 Analog input vi
RE2/CS/AN7
RE2 Digital I/O
CS Parallel Slave Port CS
AN7 Analog input 7

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More Control Systems

Martin Bates , in PIC Microcontrollers (Third Edition), 2011

Comments

The comments are delimited with a star.

use   tim.ini

This is equivalent to the include directive in the Moving picture – it incorporates a file 'tim.ini' which contains standard register labels, PortA and DircA. Port A is the 8-flake port data register and DircA the information management register (DDR).

motion.b   #$ff,DircA

Move the literal FF into the DDR to fix all $.25 as output. The '.b' means this is a byte operation (xvi- and 32-scrap words tin can be moved in the 68000). '#' ways this is a literal (immediate data in 68000 speak). '$' indicates a hex number. Note that in the 68000, a '1' in the DDR sets that flake as output – this is the opposite to the Pic.

again   motion.b   d0,PortA

The label 'again' represents a source code line address, 'd0' is the kickoff data register in a prepare of eight (d0–d7) and PortA is the output register to which the LEDs are connected.

addq   #1,d0

This means add one to (increment) d0. Surprisingly, the 68000 does not accept an increment (or decrement) instruction. 'addq' means 'add quick', used for adding a minor number to a register.

move.w   #$0fff,d1

Move a 16-bit give-and-take (westward) into d1 to initialize the delay loop.

delay   subq.w   #1,d1

Start of filibuster loop. Decrement (subtract ane from) the counter register 'd1'.

bne   filibuster

This means 'branch if not zero' to the label delay. The program jumps back and repeats the decrement until the result of the previous operation (decrement) is zero. This is bachelor in the 14-flake PIC only as a pseudo-operation.

bra   again

This is an unconditional leap equivalent to the GOTO label in PIC programs, to make the programme repeat endlessly.

Information technology can be seen that the 68000 syntax is more than complex because, first, there are more instructions and, 2nd, there are more registers and addressing modes.

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Programming Techniques

Martin Bates , in Picture show Microcontrollers (Third Edition), 2011

6.4.two Register Bank Select

The smallest PICs, including the 16F84A, have a file register set (Figure v.ii ) organized in two banks, with the most commonly used registers in the default bank 0. Some of the command registers, such as the port information direction registers, TRISA and TRISB, and the Option register, are mapped into banking concern i. Many of the special function registers (SFRs) can exist accessed in either bank. Others take used special access instructions, namely TRIS to write the port A and B data direction registers, and Selection which is used to gear up upwardly the hardware timer counter. The assembler warns that the instructions TRIS and OPTION may not be supported in future. Nevertheless, at the time writing, they still work, and provide a simplified method of banking company i access for the beginner.

Newer, more than powerful Picture 16 chips can have up to 32 banks of RAM, so a more full general method of bank selection is needed. Bank selection $.25 are provided in one of the SFRs, and these can be modified straight using BSF and BCF instructions. In the 16F84A, but one bit is needed, bit five in the status register, named RP0. Banking company 0 is enabled by default (RP0   =   0), thus bank 1 registers OPTION, TRISA, TRISB, EECON1 and EECON2 are accessed by setting RP0   =   1, prior to operating on the required annals. This explicit bank selection method is illustrated in the code fragment in the sequence beneath, which sets port B equally output:

Status   EQU     03       ; label for status annals

TRISB   EQU     86       ; label for information direction register

          BSF     Status,5 ; select bank i

          CLRW             ; load Westward with data direction code

          MOVWF TRISB   ; ready Port B equally outputs

          BCF     Status,v ; reselect   banking company   0

Information technology is a skilful idea to reselect depository financial institution 0 immediately, as this is the virtually normally used. If further banking company one admission is required, get out this pace until afterwards. In one case a bank has been selected, it remains accessible until deselected. The larger PIC chips will need additional bank select $.25.

An easier option is to use the pseudo-operation 'BANKSEL', which carries out the above process automatically:

BANKSEL   TRISB   ;   select   bank   containing TRISB,   bank   1

CLRW               ;   load   code   for all   outputs

MOVWF     TRISB ;   set up   Port   B   as   outputs

BANKSEL   PORTB ;   reselect   banking company   containing   PORTB,   bank   0

BANKSEL selects the bank that the specified register is in, and then any annals in the required bank will do. BANKSEL is effectively a predefined 'macro', a sequence of instructions that are bundled together by the assembler and invoked using a user-divers characterization. Macros are explained more fully in Section six.six, below.

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Microprocessors, instrumentation and control

Charles J. Fraser , ... (Sections 3.5.1–three.5.8), in Mechanical Engineer's Reference Book (Twelfth Edition), 1994

iii.2.4 Input/output (I/O) structure

With the microprocessor acting every bit the brain of the microcomputer system and the memory chips storing the system-operating software and application programs, the other essential hardware required is that associated with the input and output of data in essentially binary class. Interface back up fries associated with the various microprocessor families are available to enable communication with such hardware essentials every bit keyboards, display monitors, disc drives and printers.

The same I/O interface circuits are used in measurement and control applications and the main functions required of the devices are:

one.

Digital I/O logic lines which can be read or set past the microprocessor;

2.

Data direction register to configure lines as either input or output;

3.

Handshake lines to supervise data transfer via the I/O lines;

four.

Timing and counting facilities.

The software used for controlling the communication betwixt the microcomputer and other external devices is dependent upon the I/O interfacing technique employed. The 2 about mutual methods are either 'memory mapped' or 'defended port addressed'.

three.ii.4.1 Memory mapped I/O

In this method the I/O chip is continued into the system in the aforementioned way as the retention illustrated in Figure 3.1. The I/O lines are independent in groups of 8-bits termed a 'port' and this byte is addressed in the aforementioned fashion as whatsoever other location in retentiveness. The port is accessed using memory transfer instructions like PEEK and POKE in high-level Basic, or LDA and STA in low-level 6502 assembly language.

Since the interface is connected into the coach structure in exactly the aforementioned manner as the RAM and ROM, no additional decoding hardware is required. Retention addresses are, however, used up for I/O, and as a issue, communication is slower than the port addressed alternative.

3.2.4.2 Defended port addressed I/O

This method involves a 2d dedicated I/O information bus as shown in Effigy 3.2. When data are to exist input or output the necessary command signals are sent from the CPU to the I/O interface chip and the port data are transmitted via the dedicated I/O information bus. This does not effect the addressing of memory within the organization and results in faster data transfer than with the retentiveness mapped technique. The ports (or channels) are assigned unique addresses (numbers) on the dedicated jitney and are accessed using the additional software instructions of IN (or INP) and OUT in both low- and loftier-level programming languages.

Figure iii.2. Port addressed I/O

Although a number of I/O support fries are bachelor, there are essentially two which figure prominently with the memory mapped and port addressed techniques. These are the 6522 versatile interface adapter, (VIA), usually associated with the memory mapped 6502 microprocessor systems and the 8255 programmable peripheral interface, (PPI), associated with such processors every bit the 8080, Z80 and 8086 in port addressed systems.

3.ii.iv.three The 6522 VIA

This is a general interface chip which provides such interface functions as 2 8-bit parallel bi-directional ports, each with a pair of handshake lines and two 16-scrap counter timers. The ports, often designated as data registers A and B ('DRA' and 'DRB') each take an associated data direction annals ('DDRA' and 'DDRB'), which is used for setting a bit on a port as either an input or an output. The addresses follow the sequence PORTB, PORTA, DDRB and DDRA.

If a.c. or d.c. loads such every bit solenoids, motors or lamps are to be driven from the port logic bespeak levels, then a power scaling interface, such as a Darlington Driver, compatible with the microprocessor VIA must be used (see Department iii.4.1).

The VIA control lines CA1, CA2, CB1 and CB2 tin be set to operate in various read/write modes. This is achieved through the peripheral command register (PCR) in the VIA. CA1 has no output adequacy, simply CA2, CB1 and CB2 tin can all be used as either input or output. These lines are incapable, all the same, of switching a power-scaling device.

The two programmable timers within the 6522 are generally referred to every bit Tl and T2. These are xvi-bits broad and implemented as ii 8-bit registers with a low-byte/high-byte organisation. The modes of operation, selected past writing the advisable code to the auxiliary control register (ACR), are:

one.

Generate a single time interval.

two.

Generate continuous time intervals (Tl only).

iii.

Produce a single or continuous pulses of fleck 7 of DRB (Tl only).

4.

Count loftier to depression transitions on flake 6 of DRB (T2 just).

3.ii.4.iv The 8255PPI

All microprocessor families have parallel I/O interfaces and these are designed for employ with the item type of CPU. The 8255PPI is used basically with Intel 8 and sixteen-bit devices such as the 8080 and 8086/8088. The 8255PPI provides three viii-bit bi-directional ports which may be operated in three modes. No other functions such as timing or additional handshaking are available. The ports are designated as A, B and C, and information management is specified by writing to a write-only Command Register.

If hardware timing is required then a separate counter/timer device must exist used. One usually adopted with an 8255PPI 8255PPI is the Intel 8253 chip, which provides three contained 16-flake counters, each with a count rate of up to 2.6 MHz. The 8253 has various modes of operation but works basically on the same principle as the timers in the 6522 VIA.

3.2.4.5 Direct Memory Admission (DMA)

In data-conquering systems involving counterpart and digital signals suitably conditioned for inputting to a microcomputer at that place is a limitation of about 100 kHz on the sampling rate when using direct program control to transfer data to memory. If it was necessary to acquire the maximum amount of data at the highest speed, using the maximum amount of the estimator'due south resources, so the DMA technique might exist employed.

This is a hardware technique which causes the microprocessor to momentarily abandon control of the system buses so that the DMA device tin can directly access the memory. The DMA controller, connected to the I/O interface, needs to know how many bytes are to be transferred and where in memory the input data are to be stored. The data transfer rate is much faster than in an interrupt servicing method and data-sampling rates of the lodge of 1 MHz are possible for most microcomputers.

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A Simple PIC Application

Martin Bates , in PIC Microcontrollers (Third Edition), 2011

3.three.i Plan Analysis

The programme instructions must be related to the PIC internal architecture, as outlined in Chapter two, and specified in the information sheet. The instruction ready in the information sheet explains the significance of each bit in each instruction.

Accost   0000:     Didactics   =   3000     Meaning:   MOVE   zero   into   W

The lawmaking 3000 means move (copy) a literal (number given in the program) into the working register (W). All literals must exist placed initially in W before transfer to another register. The literal, which is zero in this case, can exist seen in the code as the concluding ii digits, 00.

Address   0001:     Pedagogy   =   0066     Significant:   Move   W   into   TRISB

This means copy the contents of W to the port B data management annals (TRISB). West contains 00 as a result of the first instruction. This lawmaking will set all 8 bits of register TRISB to zero, making all bits of port B operate as outputs. The file register address of port B (six) is given equally the last digit of the code. These outset two instructions are required to initialize port B for output, using the TRIS command to load the bank ane register chosen TRISB, address 86 in the file annals set.

Address   0002:     Instruction   =   0186     Meaning:   CLEAR   PORTB   to   nix

This teaching volition articulate file register half-dozen (concluding digit), which sets all bits in the port B data register (PORTB) to aught. Operations can exist carried out directly on the port data register, and the outcome will appear immediately on the LEDs in the BIN hardware or simulation.

Address   0003:     Instruction   =   0A86     Significant:   Increment   PORTB

Port B information is now modified by this education. The binary value is increased by 1, and this value volition be seen on the LEDs. This operation volition be repeated as a consequence of the next instruction (spring back), so the port LEDs will show a binary count sequence.

Accost   0004:     Instruction   =   2803     Meaning:   GOTO   last   address

This is a bound educational activity, which causes the plan to get dorsum and repeat the previous instruction. This is achieved by the pedagogy overwriting the current program counter contents with the value 03, the destination address, which is given as the terminal two digits of the pedagogy code. The execution point is thus forced back to the previous instruction, so the program keeps repeating indefinitely. Most command programs have the same bones construction as this simple example; an initialization sequence and an endless loop, which volition read the inputs and modify the outputs.

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Motion-picture show Hardware

Martin Bates , in Interfacing PIC Microcontrollers (2d Edition), 2014

i.1.3 Input and Output

Without some means of getting information and signals in and out, a data processing or digital command system would non exist very useful. Input and output ports generally contain a port data annals and a ready of command registers that let data to pass in and out. Series ports frequently use standard protocol (method of communication) to format the data.

In a PC, the keyboard, screen and mouse interfaces are the main I/O channels, supported by network, USB, SD Bill of fare and disk interfaces. The DIMM retentivity module has a parallel connector (typically 64 bits), so it attaches directly to the processor busses. This means that access is fast, because complete data blocks can be transferred at once. USB on the other paw is a series bus, and then data transfer tin only occur one bit at a time, which is inherently slower.

Microcontroller ports are generally more basic, especially in the smaller MCUs which cannot adjust the complex hardware needed for, say, a network port. The basic MCU port consists of a grouping of viii bits that can operate every bit a parallel port, but whose individual pins have alternate functions, often several. The basic parallel operation is straightforward, with an 8-bit information register that holds the I/O data, and an 8-scrap information direction register whose individual bits control the data direction, in or out. In the Motion picture, 0=output and ane=input. Alternate functions are selected in the MCU command registers at fix-upwards.

In principle, the parallel port is faster that the serial port simply uses more pins to transfer the data. The series interface must organise the data in groups of bits for manual. Dedicated registers are used to organise the data stream and control the timing of the information transfer. The serial port is based on a shift register that converts between parallel data on the internal information bus and serial information on the peripheral line. The general principles of parallel and series data transfer are shown in Figure ane.3. The block arrows represent the viii-chip internal data motorbus.

Figure ane.3. (a) Parallel and (b) serial data ports.

In the parallel port operating in output mode, the data byte is loaded from the internal data bus under the control of a read/write pulse from the CPU. The information can then be seen on the output pins by the peripheral line. For testing, a logic probe, logic analyser or just a simple LED indicator tin can be used. In input mode, data presented at the input pins from a fix of switches or other information source is latched into the annals when the port is read and is then available on the information bus for collection by the CPU. I of the functions of the port is to separate the internal information jitney from the external hardware, and some other is to temporarily shop the data. The data tin then exist transferred to memory, or otherwise candy, equally determined past the CPU program.

The serial port annals also loads data from the internal bus in parallel but and then sends it out one scrap at a time, operating every bit a shift register. If an asynchronous serial format is used, such equally RS232, start and stop $.25 are added then that bytes can be separated at the receiving cease. An error cheque fleck is also available, to permit the receiver to detect decadent data. In receive mode, the annals waits for a start bit and and so shifts in the data at the same speed equally it is sent. This means the clock rate for the ship and receive port must be the same. The USART (Universal Synchronous/Asynchronous Receive/Transmit) port, which provides RS232, volition be described in more detail later on.

A USB or network port is a more sophisticated version of the bones serial port and arranges the data bytes in packets of, perhaps, 1k bytes. These are sent in a class which is self-clocking, meaning that there is a transition within each bit (1 or 0), which triggers the bit read into the receiving register. This is synchronous data manual. An error correction code follows the data, which allows mistakes to be corrected, rather than just detected. This reduces the demand for retransmission of incorrectly received information, as required by simple error detection. Addressing information preceding the data allows multiple receivers to exist used.

The PIC 16F877A does not accept USB or network interfaces built in, so we can avoid detailed consideration of these circuitous protocols. It does nevertheless have a range of other interfaces that will be discussed in detail and sample programs are provided. If further caption of the basics of microcontroller operation is required, the reader is invited to refer to the introductory text 'PIC Microcontrollers' by the author.

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